Name
Abstract | ||
|---|---|---|
Currently, application-specific systems on chip (SoC) require complex digital designs, causing the validation process to increment, affecting the ever-narrower time-to-market. An approach to deal with this issue consists of using alreadyvalidated IP cores interconnected by a network on chip (NoC). However, the NoC is mostly used as part of an applicationspecific design, which implies wasting time in configuring the NoC for a particular application. With the aim of hiding these management problems from high-level (software) designers, in this paper, the use of a NoC as a hardware function library provider is studied. This requires the introduction of a new entity into the NoC, here called the Feeder-Collector, that acts as an intermediary between the system and the NoC. The advantages of this approach are shown by means of a case study, where an ad hoc implementation in contrasted with the proposed NoC approach, for three digital signal processing algorithms. Results show that, on average, resource of 43.68% can be achieved by using the proposed approach, while at the same time, NonRecursive- Engineering costs are reduced. |
Year | Venue | Keywords |
|---|---|---|
2013 | 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG) | Network-on-Chip, System-on-Chip, co-processor, hardware functions library, digital signal processing |
Field | DocType | ISSN |
Computer science,Parallel computing,Network on a chip,Real-time computing,Software,Dsp algorithms,Computer hardware,Digital signal processing algorithms,Embedded system | Conference | 2325-6532 |
Citations | PageRank | References |
2 | 0.44 | 6 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| B. I. Gea-Garcia | 1 | 2 | 1.11 |
| J. L. Vázquez-Avila | 2 | 6 | 1.89 |
| Remberto Sandoval-Arechiga | 3 | 6 | 2.23 |
| J. L. Pizano-Escalante | 4 | 2 | 0.44 |
| Ramon Parra-Michel | 5 | 84 | 12.86 |
| Mario Siller | 6 | 34 | 8.40 |