Paper Info
Title
Process variation tolerant all-digital multiphase DLL for DDR3 interface
Abstract
An all-digital multiphase DLL is presented that is robust to delay mismatch due to process variation. Each of four 90° phase shift blocks accurately align each phase to 90° delay using its own ring oscillator and locking delay code. Harmonic locking is protected by a ring oscillator and a counter. An area efficient binary to thermometer converter is proposed to diminish the area overhead due to four delay line controllers. An edge combiner is used for duty cycle correction and clock 2x multiplications. The measured large locking delay code difference between four 90° phase shift delay lines in the proposed DLL implemented in 45nm CMOS process, which corresponds to ±31ps at 800MHz, proves that the DLL corrects significant phase error caused by delay mismatch. Phase shift accuracy errors at 90° and 270° phases are 0.43° and 1.01°, respectively, and output frequency is 1.6GHz with 50% duty cycle at 800MHz. Power consumption is 3.3mW at 800MHz.
Year
DOI
Venue
2010
10.1109/CICC.2010.5617474
Custom Integrated Circuits Conference
Keywords
Field
DocType
CMOS integrated circuits,delay lock loops,oscillators,CMOS process,DDR3 interface,all-digital multiphase DLL,clock 2x multiplication,double data rate memory,duty cycle correction,edge combiner,frequency 1.6 GHz,frequency 800 MHz,harmonic locking,locking delay code,phase shift accuracy error,power 3.3 mW,ring oscillator,size 45 nm,thermometer converter
Delay line oscillator,Ring oscillator,Duty cycle,Computer science,Harmonic,CMOS,Group delay and phase delay,Electronic engineering,Process variation,Phase (waves)
Conference
ISSN
ISBN
Citations 
0886-5930
978-1-4244-5758-8
6
PageRank 
References 
Authors
0.67
6
7
Name
Order
Citations
PageRank
Heechai Kang1152.06
Kyungho Ryu210011.72
Dong-Hwan Lee313513.77
Won Lee4142.05
SuHo Kim5141.37
JongRyun Choi6142.38
Seong-ook Jung733253.74