Name
Abstract | ||
|---|---|---|
As the number of cores increases in both incoming and future chip multiprocessors, coherence protocols must address novel hardware structures in order to scale in terms of performance, power, and area. It is well known that most blocks accessed by parallel applications are private (i.e., accessed by a single core). These blocks present different directory requirements and behavior than shared blocks. Based on this fact, this paper proposes a two-level directory cache that tracks shared blocks in a small and fast first-level cache and private blocks in a larger and slower second-level cache, namely Shared and Private caches, respectively. Speed and area reasons suggest the use of eDRAM technology much dense but slower than SRAM technology for the Private cache, which in turn brings energy savings. Experimental results for a 16-core system show improvements in performance by 11.1%, in area by 25.4%, and in energy consumption by 20.5% compared to a conventional directory cache. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2370816.2370891 | PACT |
Keywords | DocType | ISSN |
blocks present different directory,scalable two-level directory cache,sram technology,slower second-level cache,edram technology,conventional directory cache,area reason,two-level directory cache,first-level cache,energy consumption,private cache,multicore,cache coherence | Conference | 1089-795X |
ISBN | Citations | PageRank |
978-1-5090-6609-4 | 6 | 0.41 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joan J. Valls | 1 | 9 | 1.83 |
| Alberto Ros | 2 | 384 | 32.60 |
| Julio Sahuquillo | 3 | 420 | 53.71 |
| María E. Gómez | 4 | 115 | 5.70 |
| José Duato | 5 | 3481 | 294.85 |