Paper Info
Title
RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT
Abstract
In this paper, two different FPGA implementations of the lightweight cipher PRESENT are proposed. The main design strategy for both designs is the utilization of existing RAM blocks in FPGAs for the storage of internal states, thereby reducing the slice count. In the first design, S-boxes are realized within the slices, while in the second design they are also integrated into the same RAM block used for state storage. Both designs are well suited for lightweight applications, which are implemented on low-cost FPGA/CPLD devices. Besides low-area, a reasonable throughput is also obtained even though it is not the first concern. In addition to a single block RAM, the two designs occupy only 83 and 85 slices and produce a throughput of 6.03 and 5.13 Kbps at 100 KHz system clock on a Xilinx Spartan XC3S50 device, respectively.
Year
DOI
Venue
2011
10.1109/ReConFig.2011.74
Reconfigurable Computing and FPGAs
Keywords
Field
DocType
low-cost fpga,cpld device,lightweight cipher present,main design strategy,state storage,lightweight application,single block,ram block,ram-based ultra-lightweight fpga implementation,reasonable throughput,different fpga implementation,algorithm design,ram,field programmable gate array,security,algorithm design and analysis,field programmable gate arrays,throughput,radiofrequency,fpga,registers
Spartan,Design strategy,Block ram,Algorithm design,Complex programmable logic device,Computer science,Parallel computing,Field-programmable gate array,System time,Throughput,Computer hardware,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4577-1734-5
9
0.78
References 
Authors
11
2
Name
Order
Citations
PageRank
Elif Bilge Kavun11149.89
Tolga Yalçin21209.20