Paper Info
Title
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
Abstract
An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (25 inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the...
Year
DOI
Venue
2003
10.1109/JSSC.2002.807405
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Phase locked loops,Frequency conversion,Clocks,Phase detection,Detectors,Pulse inverters,CMOS integrated circuits,High speed integrated circuits,Digital control,Oscillators
Journal
38
Issue
ISSN
Citations 
2
0018-9200
16
PageRank 
References 
Authors
2.19
5
2
Name
Order
Citations
PageRank
T. Watanabe125251.28
S. Yamauchi2162.19