Name
Abstract | ||
|---|---|---|
Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA. © Springer Science+Business Media, LLC 2012. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/s11227-012-0810-x | The Journal of Supercomputing |
Keywords | Field | DocType |
Multiprocessor system on chip,Star network,Network on chip,Programming interfaces | System on a chip,Star network,Shared memory,Computer science,Parallel computing,Network on a chip,Field-programmable gate array,Multiprocessing,MPSoC,Speedup,Embedded system,Distributed computing | Journal |
Volume | Issue | ISSN |
62 | 3 | 15730484 |
Citations | PageRank | References |
13 | 0.67 | 36 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chao Wang | 1 | 35 | 2.86 |
| Xi Li | 2 | 202 | 36.61 |
| Junneng Zhang | 3 | 97 | 8.85 |
| Xuehai Zhou | 4 | 551 | 77.54 |
| Aili Wang | 5 | 31 | 2.83 |