Name
Abstract | ||
|---|---|---|
This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transfun.E94.A.937 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
digital signal processing (DSP), FIR, filter, architecture, cubic spline, interpolation, digital TV (DTV) | Root-raised-cosine filter,Half-band filter,Computer science,Real-time computing,Multiplexer,Theoretical computer science,Adaptive filter,Finite impulse response,Computer hardware,Cascaded integrator–comb filter,Clock rate,Filter design | Journal |
Volume | Issue | ISSN |
E94A | 3 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| YongKyu Kim | 1 | 4 | 1.49 |
| Changseok Choi | 2 | 33 | 7.39 |
| Hanho Lee | 3 | 205 | 40.92 |