Name
Abstract | ||
|---|---|---|
This paper describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ITC.2004.201 | ITC |
Keywords | Field | DocType |
new compressed scan technology,one-pass virtualscan atpg,easy-to-implement solution,test cost reduction,aliasing effects algorithmically,additional circuitry,virtualscan atpg avoids unknown-value,virtualscan circuit,maximum test compaction,test pattern,virtualscan technology,integrated circuit design,virtual reality,automatic test pattern generation,chip | Boundary scan,Automatic test pattern generation,Automatic test equipment,Computer science,Circuit extraction,Scan chain,Electronic engineering,Integrated circuit design,Computer hardware,Test compression,Cost reduction | Conference |
ISBN | Citations | PageRank |
0-7803-8581-0 | 49 | 2.25 |
References | Authors | |
18 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Laung-terng Wang | 1 | 601 | 44.22 |
| Khader S. Abdel-Hafez | 2 | 124 | 5.88 |
| Shianling Wu | 3 | 165 | 26.85 |
| Xiaoqing Wen | 4 | 790 | 77.12 |
| Hiroshi Furukawa | 5 | 211 | 31.32 |
| Fei-Sheng Hsu | 6 | 50 | 2.65 |
| Shyh-Horng Lin | 7 | 66 | 3.60 |
| Sen-Wei Tsai | 8 | 49 | 2.25 |