Name
Abstract | ||
|---|---|---|
This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz-50MHz frequency range, the input dynamic range is wider than 70 dB within +/- 2 dB linearity error. The chip occupies an area of 0.7 mm(2) x 0.3mm(2) using a 0.18-mu m CMOS. It draws 1.3mA from a 1.8V supply. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1142/S0218126613400343 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
CMOS,low-power,weak-inversion,receiving signal strength indicator (RSSI),limiting amplifier (LA) | Rectification,Dynamic range,Detection theory,Computer science,Operational transconductance amplifier,Voltage,CMOS,Chip,Electronic engineering,Electrical engineering,Amplifier | Journal |
Volume | Issue | ISSN |
22 | SP10 | 0218-1266 |
Citations | PageRank | References |
4 | 0.49 | 5 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keping Wang | 1 | 8 | 4.42 |
| XueMei Lei | 2 | 4 | 0.83 |
| Kaixue Ma | 3 | 38 | 19.01 |
| Kiat Seng Yeo | 4 | 365 | 63.72 |
| Xiang Cao | 5 | 1459 | 83.46 |
| Zhigong Wang | 6 | 29 | 21.30 |