Name
Abstract | ||
|---|---|---|
With the development of semiconductor technology, multicore is integrated on one chip [1]. In CMP, more than one core accessing the shared data will cause memory access conflict and the problem of cache coherence. Cache coherence is a precondition for the system to function correctly. So it is a key problem in CMP. In this paper, we propose a new pseudo sharing level one data cache in a chip multiprocessor architecture (PSDMP). In PSDMP, the request of memory access will be propagated on a ring chain. This method can reduce both the complexity of the design and the load of L2 cache. Simulation results show that performance of PSDMP improves about 30% averagely than another CMP which uses MESI protocol, especially the best is about 100% for the parallel applications which has many inter-processor communications for modifying shared data. In one word, PSDMP is promising processor architecture. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/11942634_6 | ISPA Workshops |
Keywords | Field | DocType |
cache coherence,key problem,shared data,chip multiprocessor architecture,memory access conflict,promising processor architecture,data cache,memory access,pseudo share data cache,mesi protocol,l2 cache,chip,processor architecture | Cache invalidation,Cache pollution,MESIF protocol,Computer science,Cache,Parallel computing,MESI protocol,Cache algorithms,Cache coloring,Bus sniffing | Conference |
Volume | ISSN | ISBN |
4331 | 0302-9743 | 3-540-49860-5 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pengyong Ma | 1 | 1 | 1.70 |
| Xiao Hu | 2 | 4 | 2.54 |
| Shuming Chen | 3 | 138 | 38.21 |
| Yang Guo | 4 | 67 | 32.72 |