Name
Abstract | ||
|---|---|---|
The paper presents a hybrid architecture for digital polar-to-Cartesian (i.e. phase-to-I/Q) designs. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources. FPGA resource utilization, timing and power consumption as well as accuracy of calculated results may be optimised consistently in comparison to conventional pure CORDIC algorithm implementations. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/978-3-540-30117-2_102 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
resource utilization | Logic synthesis,Lookup table,Architecture,Computer science,Parallel computing,Circuit design,Field-programmable gate array,Implementation,CORDIC,Computer hardware,Energy consumption,Embedded system | Conference |
Volume | ISSN | Citations |
3203 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ireneusz Janiszewski | 1 | 2 | 1.10 |
| Hermann Meuth | 2 | 125 | 38.64 |
| Bernhard Hoppe | 3 | 3 | 2.16 |