Paper Info
Title
Bridging The Computation Gap Between Programmable Processors And Hardwired Accelerators
Abstract
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor while trading off as little as 2x power and area efficiency to the non-programmable accelerator
Year
DOI
Venue
2009
10.1109/HPCA.2009.4798266
HPCA-15 2009: FIFTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS
Keywords
Field
DocType
asic,application specific integrated circuit,application specific integrated circuits,new media,power efficiency,schedules,computer architecture,mobile device,registers,field programmable gate arrays,signal processing,hardware,reduced instruction set computing
Electrical efficiency,Signal processing,Computer science,OpenRISC,Parallel computing,Field-programmable gate array,Application-specific integrated circuit,Compiler,Real-time computing,Reduced instruction set computing,Integrated circuit
Conference
ISSN
Citations 
PageRank 
1530-0897
42
2.68
References 
Authors
17
4
Name
Order
Citations
PageRank
Kevin Fan133520.29
Manjunath Kudlur2199771.21
Ganesh S. Dasika338724.30
Scott Mahlke44811312.08