Name
Abstract | ||
|---|---|---|
The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic脗® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1147/rd.466.0691 | IBM Journal of Research and Development |
Keywords | Field | DocType |
system on a chip | Analysis tools,IBM,Systems engineering,System on a chip design,Computer science,System requirements | Journal |
Volume | Issue | ISSN |
46 | 6 | 0018-8646 |
Citations | PageRank | References |
22 | 2.55 | 7 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| John A. Darringer | 1 | 277 | 206.31 |
| R. A. Bergamaschi | 2 | 174 | 16.90 |
| Subhrajit Bhattacharya | 3 | 22 | 2.55 |
| D. Brand | 4 | 292 | 84.65 |
| Andreas Herkersdorf | 5 | 31 | 4.54 |
| Joseph K. Morrell | 6 | 23 | 2.96 |
| I. Nair | 7 | 31 | 3.09 |
| Patricia Sagmeister | 8 | 22 | 2.55 |
| Youngsoo Shin | 9 | 836 | 93.86 |