Title
A hybridized genetic parallel programming based logic circuit synthesizer
Abstract
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system integrating GPP and FlowMap, a Hybridized GPP based Logic Circuit Synthesizer (HGPPLCS) is developed. To show the effectiveness of the proposed HGPPLCS, six combinational logic circuit problems are used for evaluations. Each problem is run for 50 times. Experimental results show that both the lookup table counts and the propagation gate delays of the circuits collected are better than those obtained by conventional design or evolved by GPP alone. For example, in a 6-bit one counter experiment, we obtained combinational digital circuits with 8 four-input lookup tables in 2 gate level on average. It utilizes 2 lookup tables and 3 gate levels less than circuits evolved by GPP alone.
Year
DOI
Venue
2006
10.1145/1143997.1144145
GECCO
Keywords
Field
DocType
four-input lookup table,lookup table count,hybridized genetic parallel programming,combinational logic circuit problem,propagation gate delay,lookup table,genetic parallel programming,logic circuit synthesizer,combinational digital circuit,gpp paradigm,gate level,hybridized gpp,local search,system integration,genetics,field programmable gate array,digital circuits
Lookup table,Logic gate,Digital electronics,Computer science,Parallel computing,Field-programmable gate array,Genetic programming,Combinational logic,Local search (optimization),Electronic circuit
Conference
ISBN
Citations 
PageRank 
1-59593-186-4
1
0.35
References 
Authors
0
3
Name
Order
Citations
PageRank
Wai Shing Lau130.85
Kin Hong Lee2506.56
Kwong-Sak Leung31887205.58