Paper Info
Title
HEURISTIC TECHNOLOGY MAPPER FOR LUT BASED FPGAs
Abstract
ONE OF MAIN OBJECTIVE IN THE PROCESS OF MAPPING A CIRCUIT ONTO A LOOK-UP TABLE(LUT) BASED FPGA IS TO MINIMIZE THE NUMBER OF LUTs REQUIRED TO IMPLEMENT THE CIRCUIT. A NEW TOP-DOWN TECHNOLOGY MAPPER ALGORITHM IS DISCUSSED IN THIS PAPER WHICH AIMS AT MINIMIZING NUMBER OF LUTs NEEDED FOR MAPPING THE DIGITAL CIRCUIT. THE ALGORITHM MAKES USE OF COMBINATION OF NODE SELECTION AND COVERING HEURISTICS USING WHICH MAXIMUM NUMBER OF DAG NODES ARE COVERED BY A SELECTED LUT.INITIALLY THE GIVEN CIRCUIT IS CONVERTED INTO A DAG REPRESENTATION. LATER THIS DAG IS CONVERTED TO A K-RESTRICTED DAG USING A PRE-PROCESSOR. THIS K-RESTRICTED DAG IS NEXT TOPOLOGICALLY SORTED. K-RESTRICTED TOPOLOGICALLY ORDERED DAG IS NOW SCANNED FROM PO AND TO PI END IN LEVEL BY LEVEL FASHION SUCH THAT A LUT COVERS MAXIMUM NUMBER OF NODES OF DAG AT EACH STEP. IN THIS PROCESS ALGORITHM LOOKS FOR 4 CATEGORIES OF NODES FOR COVERING PURPOSE. THESE ARE (A)PI NODE WITH OUTDEGREE=1 (B)PI NODE WITH OUTDEGREE1 (C)NON-PI NODE WITH OUTDEGREE1 AND (D) NON-PI NODE WITH OUTDEGREE=1. DIFFERENT ACTIONS ARE TAKEN ON EACH CATEGORY OF NODES.THE RESULTS OBTAINED BY THIS ALGORITHM WERE FOUND TO BE BETTER THAN THOSE OBTAINED BY CHORTLE, LEVEL-MAP AND FLOW-MAP-R TECHNOLOGY MAPPER ALGORITHMS FOR MAJORITY OF BENCHMARK CIRCUITS.
Year
DOI
Venue
1999
10.1109/ICVD.1999.745187
VLSI Design
Keywords
Field
DocType
pi node,dag nodes,non-pi node,a dag representation,heuristic technology mapper,mapping a circuit onto,lut based fpgas,k-restricted topologically ordered dag,k-restricted dag,k-restricted dag using a,a selected lut,a look-up table,fpga,look up table,combinational circuits,lut,digital circuits,logic circuits,logic synthesis,field programmable gate arrays,network synthesis,logic gates,directed graphs,production,field programmable gate array,logic design,directed acyclic graph,top down
Logic synthesis,Lookup table,Digital electronics,Logic optimization,Computer science,Programmable logic array,Field-programmable gate array,Electronic engineering,Register-transfer level,Programmable logic device
Conference
ISBN
Citations 
PageRank 
0-7695-0013-7
0
0.34
References 
Authors
4
2
Name
Order
Citations
PageRank
Chitrasena Bhat100.34
Niranjan N. Chiplunkar242.50