Title
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.
Year
DOI
Venue
2012
10.1109/ESSCIRC.2012.6341354
ESSCIRC
Keywords
Field
DocType
jitter,phase locked loops,electronics packaging,system on a chip
Dram,System on a chip,Computer science,Latency (engineering),Electronic engineering,Input/output,Bandwidth (signal processing),Computer hardware,Memory rank,SerDes,Random access
Conference
Citations 
PageRank 
References 
1
0.42
4
Authors
39