Title
A 800 MHz System-on-Chip for Wireless Infrastructure Applications
Abstract
The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2™ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.
Year
DOI
Venue
2004
10.1109/ICVD.2004.1260953
VLSI Design
Keywords
Field
DocType
c64x vliwdsp velociti,wireless infrastructure applications,mhz system-on-chip,o bandwidthof,2-level memory system,16-bit mmacs,nm cmos technology,7-layer coppermetalization,high performancewireless infrastructure application,8-bit mmacs,8-way vliwdsp core,copper,cmos integrated circuits,forward error correction,system on a chip,vliw,acceleration,cu,cmos technology,system on chip,digital signal processing,arithmetic,computer architecture,decoding,chip,registers
Digital signal processing,System on a chip,Wireless,Very long instruction word,Computer science,8-bit,Electronic engineering,CMOS,Chip,Bandwidth (signal processing),Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2072-3
2
0.47
References 
Authors
4
24