Name
Abstract | ||
|---|---|---|
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing problem is evident from the non-trivial number of structurally testable while functionally untestable (ST-FU) faults. Such faults can be detected by some scan/BIST patterns but not by any functional pattern. The goal of this BIST scheme is to allow only functional-like patterns generated from the BIST random test pattern generator (RTPG) as tests. This is done by inserting a Monitor at the output of the RTPG, which indicates whether the current pattern violates some pre-extracted functional constraints. In case of violation, the pattern is skipped. In our implementation, a SAT solver is used to analyze and extract a set of functional constraints from the functional logic. These functional constraints are then implemented in hardware as the Monitor. Even though the extracted functional constraints can not be exhausted, the proposed BIST scheme can detect and filter out, in real-time, a substantial subset of the nonfunctional patterns, and thus minimizing the over-testing problem. We present some experimental results to demonstrate the effectiveness of the proposed BIST scheme. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/VTS.2005.69 | VTS |
Keywords | Field | DocType |
logic bist,crosstalk-induced failures,functional constraints,structurally testable while functionally untestable faults,functional pattern,bist random test pattern,proposed bist scheme,bist pattern,random test pattern generator,automatic test pattern generation,delays,scan-based bist,built-in self test,crosstalk,bist scheme,pseudofunctional bist,functional constraint,functional logic,over-testing problem,pseudo-functional bist scheme,pseudo-functional scan-based bist,delay fault,sat solver,delay failures,logic testing,testing,real time,logic,random testing,fault detection,hardware | Automatic test pattern generation,Logic testing,Computer science,Crosstalk,Boolean satisfiability problem,Real-time computing,Electronic engineering,Test pattern generators,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2314-5 | 5 |
PageRank | References | Authors |
0.46 | 17 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yung-Chieh Lin | 1 | 167 | 10.50 |
| Feng Lu | 2 | 174 | 12.25 |
| Kwang-Ting Cheng | 3 | 5755 | 513.90 |