Name
Abstract | ||
|---|---|---|
This paper describes a 16:1 multiplexer using 0.18 /spl mu/m SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dis... |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/4.841503 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Multiplexing,Circuits,Capacitance,CMOS technology,Paper technology,Pipelines,Large scale integration,Data processing,SONET,Gallium arsenide | Journal | 35 |
Issue | ISSN | Citations |
5 | 0018-9200 | 1 |
PageRank | References | Authors |
0.39 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| toru nakura | 1 | 1 | 0.39 |
| kazunori ueda | 2 | 1 | 0.39 |
| keishi kubo | 3 | 1 | 0.39 |
| Y. Matsuda | 4 | 26 | 11.67 |
| K. Mashiko | 5 | 49 | 9.50 |
| Tsutomu Yoshihara | 6 | 26 | 8.48 |