Paper Info
Title
Subthreshold parallel FM-to-digital Δ-Σ converter with output-bit-stream addition by interleaving
Abstract
Single and parallel subthreshold frequency-modulation-to-digital Δ-Σ modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional parallel FDSM, reduces power, area, and complexity at the cost of using clocks with higher speed in its output stage. In addition, compared to the single FDSM, the parallel converter shows an improvement in signal-to-quantization-noise ratio of more than 25 dB at supply voltages as low as 300 mV.
Year
DOI
Venue
2009
10.1109/TCSI.2008.2010107
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Keywords
DocType
Volume
90-nm CMOS technology,parallel subthreshold frequency-modulation-to-digital,higher speed,output-bit-stream addition,signal-to-quantization-noise ratio,output stage,bit-stream addition,parallel converter,conventional parallel FDSM,single FDSM,parallel FM-to-digital,512-stage parallel FDSM
Journal
56
Issue
ISSN
Citations 
8
1549-8328
0
PageRank 
References 
Authors
0.34
4
2
Name
Order
Citations
PageRank
Francesco Cannillo1103.70
Christofer Toumazou226559.06