Title
Rapid Prototyping Of The Data-Driven Chip-Multiprocessor (D-2-Cmp) Using Fpgas
Abstract
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D-2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.
Year
DOI
Venue
2008
10.1142/S0129626408003399
PARALLEL PROCESSING LETTERS
Keywords
Field
DocType
Data-Driven Multithreading, FPGA, Multicore
Multithreading,Computer science,Parallel computing,FPGA prototype,Field-programmable gate array,Thread (computing),Synchronization (computer science),PowerPC,Multi-core processor,Operating system,Reconfigurable computing
Journal
Volume
Issue
ISSN
18
2
0129-6264
Citations 
PageRank 
References 
0
0.34
14
Authors
5
Name
Order
Citations
PageRank
Konstantinos Tatas19816.40
Costas Kyriacou2656.57
Paraskevas Evripidou331334.69
Pedro Trancoso437743.79
Stephan Wong500.34