Name
Abstract | ||
|---|---|---|
Despite the fact that retiming circuits have a large potential (especially in automatically synthesized circuits from higher-level descriptions) it has not been widely included in the current design methodologies. One of the main problems is finding an equivalent initial state for the retimed logic. In this paper we introduce a new reverse retiming algorithm which will find a retiming for a given cycle time, if one exists. This new algorithm minimizes the effort required to find equivalent initial states and reduces the chance that the network needs to be modified to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings preserving the initial state condition. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/EDTC.1995.470405 | EDTC '95 Proceedings of the 1995 European conference on Design and Test |
Keywords | Field | DocType |
equivalent initial state,logic cad,retimed logic,reversed retiming algorithm,large potential,new algorithm,new reverse,higher-level description,improving initialization,circuit optimisation,retiming circuit,current design methodology,initialization,initial state condition,cycle time,reversed retiming,new efficient retiming method,timing,sequential circuits,retiming circuits,registers,design methodology,kernel,logic | Kernel (linear algebra),Retiming,Sequential logic,Computer science,Algorithm,Real-time computing,Electronic engineering,Initialization,Electronic circuit | Conference |
ISSN | ISBN | Citations |
1066-1409 | 0-8186-7039-8 | 6 |
PageRank | References | Authors |
0.80 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stok, L. | 1 | 13 | 1.31 |
| Spillinger, I. | 2 | 14 | 11.03 |
| G. Even | 3 | 100 | 7.19 |