Paper Info
Title
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
Abstract
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of recent communication protocols which frequently use complicated mechanisms such as mutual exclusion and dynamic job assignment, the proposed model is expected to reduce development cost in designing/developing such protocols. We implement specifications described in the model so that EFSMs work synchronously with the same clock, and that the synchronization mechanism for checking executability of each tuple of synchronizing transitions is implemented as a combinational logic circuit. Through some experiments, we have confirmed that the proposed technique can synthesize hardware circuits with relatively good performances for practical use.
Year
DOI
Venue
2000
10.1145/337292.337771
DAC
Keywords
Field
DocType
high-level synthesis,multi-way synchronization,concurrent efsms,practical use,communication protocols,communication protocol,hardware implementation,efsms work synchronously,synchronization mechanism,proposed technique,mutli-way synchronization,hardware circuit,recent communication protocol,lotos,high level synthesis,hardware,combinational circuits,network synthesis,synchronization,mutual exclusion,job design
Permission,Synchronization,Tuple,Computer science,High-level synthesis,Synchronizing,Combinational logic,Real-time computing,Mutual exclusion,Embedded system,Communications protocol,Distributed computing
Conference
ISSN
ISBN
Citations 
0738-100X
1-58113-187-9
14
PageRank 
References 
Authors
0.90
7
5
Name
Order
Citations
PageRank
Hisaaki Katagiri1181.40
Keiichi Yasumoto2670110.78
Akira Kitajima3918.69
Teruo Higashino41086119.60
kenichi taniguchi525635.56