A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter.

Paper Info

Title
A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter.

Year	DOI	Venue
2012	10.1109/ESSCIRC.2012.6341333	european solid-state circuits conference
Keywords	Field	DocType
cmos integrated circuits,jitter,phase locked loops,cmos technology,phase noise	Phase-locked loop,Sub-sampling,Computer science,Phase noise,Voltage-controlled oscillator,Figure of merit,CMOS,Electronic engineering,Jitter,dBc,Electrical engineering	Conference
Citations	PageRank	References
7	0.64	4
Authors
3

Authors (3 rows)

Cited by (7 rows)

References (4 rows)

Name	Order	Citations	PageRank
Kenta Sogo	1	7	0.98
Akihiro Toya	2	9	3.75
Takamaro Kikkawa	3	69	14.32