Name
Abstract | ||
|---|---|---|
A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speeding up the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/VTEST.1997.600264 | VTS |
Keywords | Field | DocType |
sequential circuits,method utilizes circuit netlist,diagnostic test generation,sequential circuit,modified circuit,forced value,computational effort,diagnostic atpg process,conventional test generator,diagnostic test pattern generation,primary input,diagnostic test,vlsi | Stuck-at fault,Automatic test pattern generation,Netlist,Sequential logic,Fault coverage,Computer science,Scan chain,Electronic engineering,Test compression,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-7810-0 | 27 |
PageRank | References | Authors |
1.57 | 18 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ismed Hartanto | 1 | 240 | 16.76 |
| Vamsi Boppana | 2 | 267 | 20.98 |
| J. H. Patel | 3 | 4577 | 527.59 |
| W. Kent Fuchs | 4 | 1469 | 279.02 |
| hartanto@dtc. hp. com | 5 | 27 | 1.57 |