Name
Title | ||
|---|---|---|
High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC |
Abstract | ||
|---|---|---|
This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietfec/e89-a.4.916 | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Keywords | Field | DocType |
high frequency analog signal,next-generation radio system,rf dac,high-speed continuous-time subsampling bandpass,matlab simulation,ad modulator architecture employing,sampling clock jitter,continuous-time bandpass,alleviates excess loop delay,radio frequency dac,high-accuracy ad conversion,ad modulator architecture,jitter,bandpass,radio frequency,high frequency | Architecture,Band-pass filter,Modulation,Radio frequency,Sampling (statistics),Jitter,Analog signal,Electrical engineering,Mathematics,Matlab simulation | Journal |
Volume | Issue | ISSN |
E89-A | 4 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masafumi Uemori | 1 | 0 | 0.68 |
| Haruo Kobayashi | 2 | 38 | 25.15 |
| Tomonari Ichikawa | 3 | 0 | 0.68 |
| Atsushi Wada | 4 | 2 | 2.31 |
| Koichiro Mashiko | 5 | 2 | 2.31 |
| Toshiro Tsukada | 6 | 20 | 4.74 |
| Masao Hotta | 7 | 30 | 9.59 |