Name
Abstract | ||
|---|---|---|
Proposes a transistor placement algorithm to generate standard cell layout in a 2D placement style that is not restricted to row-based transistor placement. The cost function constructed for transistor placement optimization is able to optimize wirings directly and diffusion sharing indirectly but sufficiently. This transistor placement algorithm, applied to several standard cells, has demonstrated the capability to generate a nearly-optimal 2D placement that is comparable to manually designed placement. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/ASPDAC.1997.600335 | Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference |
Keywords | Field | DocType |
2D transistor placement algorithm,cell synthesis,standard cell layout generation,row-based transistor placement,cost function,diffusion sharing optimization,wiring optimization | Integrated circuit layout,Algorithm design,Computer science,Transistor circuits,Placement,Electronic engineering,Standard cell,Electronic circuit,Transistor | Conference |
ISBN | Citations | PageRank |
0-7803-3662-3 | 1 | 0.39 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shunji Saika | 1 | 1 | 0.39 |
| Masahiro Fukui | 2 | 42 | 14.57 |
| Noriko Shinomiya | 3 | 5 | 0.84 |
| Toshiro Akino | 4 | 18 | 15.05 |