Name
Abstract | ||
|---|---|---|
In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and master-slave flip-flop were designed and optimized for high-speed operation. Using these gates, we propose three different 8-bit MCML binary-tree multiplier architectures and compare their performance in terms of latency, throughput (number of multiplications per second) and power consumption. According to our simulation, the fastest multiplier targeting for TSMC 0.18 mum CMOS technology attains a throughput of 4.76 GHz or 4.76 Billion multiplications per second and a latency of 3.8 ns. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329389 | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS |
Keywords | Field | DocType |
compressors,throughput,binary tree,logic design,full adder,adders,logic gates,logic gate,cmos technology,master slave,compressor | Logic synthesis,Logic gate,XNOR gate,Adder,Computer science,Electronic engineering,NAND gate,Multiplier (economics),CMOS,Current-mode logic | Conference |
Citations | PageRank | References |
3 | 0.52 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Venkat Srinivasan | 1 | 20 | 5.79 |
| Dong Sam Ha | 2 | 423 | 54.45 |
| Jos Sulistyo | 3 | 3 | 0.86 |