Name
Abstract | ||
|---|---|---|
Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/HPCA.2013.6522335 | HPCA |
Keywords | Field | DocType |
state-of-the-art routers,ts-router,critical pipeline stage,noc router,qoa,network routing,novel router design,power consumption,network-on-chip router,verilog,hardware description languages,quality-of-allocation,matching decisions,output port resources,prior allocation,matching decision,allocation decision,input request,real benchmark programs,future request,input port,network-on-chip,lightweight fashion,on-chip network,time series,switch allocation,efficient router design,pipeline processing,network on chip | Latency (engineering),Computer science,Bridge router,Computer network,Real-time computing,Core router,Verilog,Distributed computing,Hardware description language,Parallel computing,Network on a chip,Router,One-armed router | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-4673-5585-8 | 5 |
PageRank | References | Authors |
0.45 | 22 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuan-Ying Chang | 1 | 24 | 3.03 |
| Yoshi Shih-Chieh Huang | 2 | 31 | 2.73 |
| Matthew Poremba | 3 | 78 | 5.46 |
| Narayanan Vijaykrishnan | 4 | 6955 | 524.60 |
| Yuan Xie | 5 | 6430 | 407.00 |
| Chung-Ta King | 6 | 450 | 74.71 |