Name
Abstract | ||
|---|---|---|
We present a novel VLSI architecture for division and multiplication in GF(2m), aimed at applications in low cost elliptic curve cryptographic processors. A compact and fast arithmetic unit (AU) was designed which uses substructure sharing between a modified version of the binary extended greatest common divisor (GCD) and the most significant bit first (MSB-first) multiplication algorithms. This AU produces division results at a rate of one per 2m–1 clock cycles and multiplication results at a rate of one per m clock cycles. Analysis shows that the computational delay time of the proposed architecture for division is significantly less than previously proposed bit-serial dividers and has the advantage of reduced chip area requirements. Furthermore, since this novel architecture does not restrict the choice of irreducible polynomials and has the features of regularity and modularity, it provides a high degree of flexibility and scalability with respect to the field size m. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11557654_61 | high performance computing |
Keywords | Field | DocType |
novel architecture,novel VLSI architecture,multiplication algorithm,division result,m clock cycle,low cost cryptographic application,bit-serial divider,field size m,novel arithmetic unit,clock cycle,proposed architecture,multiplication result | Most significant bit,Finite field,Multiplication algorithm,Computer science,Arithmetic,Multiplication,Greatest common divisor,Divisor,GF(2),Binary number | Conference |
Volume | ISSN | ISBN |
3726 | 0302-9743 | 3-540-29031-1 |
Citations | PageRank | References |
1 | 0.40 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chang Hoon Kim | 1 | 73 | 9.02 |
| Chun Pyo Hong | 2 | 73 | 9.02 |
| Soonhak Kwon | 3 | 170 | 22.00 |