Name
Abstract | ||
|---|---|---|
An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2001238 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
non-uniform wire,low power,proposed methodology,dynamic power consumption,tight area constraint,detailed routing,promising power reduction,optimization methodology,wire topology optimization,area investment,wire power reduction,non-uniform spacing,microelectronics,network topology,investments,network routing,low power electronics,routing,design flow,cmos integrated circuits,topology optimization,capacitance,topology | Computer science,Network topology,Electronic engineering,Design flow,CMOS,Dynamic demand,Topology optimization,Whitespace,Energy consumption,Electrical engineering,Low-power electronics | Journal |
Volume | Issue | ISSN |
17 | 1 | 1063-8210 |
Citations | PageRank | References |
3 | 0.43 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paul Zuber | 1 | 6 | 1.19 |
| Othman Bahlous | 2 | 3 | 0.43 |
| Thomas Ilnseher | 3 | 44 | 2.49 |
| Michael Ritter | 4 | 7 | 1.25 |
| Walter Stechele | 5 | 365 | 52.77 |