Name
Abstract | ||
|---|---|---|
A first study of the BTI reliability of a 6Å EOT CMOS process for potential application in sub-threshold logic is presented. Considerable threshold voltage shifts are observed also for sub-threshold operation. The observed shifts convert to a remarkable current reduction due to the exponential dependence of current on Vth in this operating regime. Moreover, the pMOS is observed to degrade significantly more w.r.t. the nMOS device, inducing a detrimental Vth-imbalance. A proper device failure criterion is proposed, based on simulation of the DC robustness of an inverter logic circuit. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1016/j.microrel.2012.06.058 | Microelectronics Reliability |
Field | DocType | Volume |
Inverter,Logic gate,Exponential function,NMOS logic,Electronic engineering,Cmos process,Robustness (computer science),Engineering,PMOS logic,Electrical engineering,Threshold voltage,Reliability engineering | Journal | 52 |
Issue | ISSN | Citations |
9 | 0026-2714 | 1 |
PageRank | References | Authors |
0.36 | 4 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jacopo Franco | 1 | 22 | 18.53 |
| S. Graziano | 2 | 1 | 0.36 |
| Ben Kaczer | 3 | 49 | 12.50 |
| Felice Crupi | 4 | 25 | 8.33 |
| L-Å Ragnarsson | 5 | 6 | 3.66 |
| Tibor Grasser | 6 | 68 | 12.77 |
| Guido Groeseneken | 7 | 59 | 23.15 |