Name
Abstract | ||
|---|---|---|
Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows: (a) to read AER interchip traffic; and (b) inject a sequence of events to the AER structure. This paper presents a PCI to AER interface, that dispatches a sequence of events with timing information. It is able to recovery the possible delays introduced by AER bus. It has been implemented in real time hardware using VHDL and tested in a PCI-AER board, developed by authors, that currently capable to send and receive events at a peak rate of 16 Mev/sec, and a typical rate of 10 Mev/sec |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693296 | Island of Kos |
Keywords | Field | DocType |
hardware description languages,neural chips,peripheral interfaces,AER bus,PCI-AER interface,VHDL,address event representation,neuro-inspired spiking systems,neuromorphic interchip communication protocol,real time hardware | Conventional PCI,Computer science,Neuromorphic engineering,Electronic engineering,VHDL,Multiplexing,Electronic circuit,Hardware description language,Embedded system,Communications protocol,Interface (computing) | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 2 |
PageRank | References | Authors |
0.48 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Paz-vicente | 1 | 56 | 6.43 |
| Alejandro Linares-barranco | 2 | 473 | 53.18 |
| Cascado, D. | 3 | 29 | 5.23 |
| Miguel A. Vega-Rodriguez | 4 | 145 | 18.81 |
| Gabriel Jiménez | 5 | 87 | 10.18 |
| Antón Civit | 6 | 135 | 19.32 |
| José Luis Sevillano | 7 | 90 | 14.26 |
| Linares-Barranco, A. | 8 | 144 | 9.02 |