Abstract | ||
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Adopting a non-canonical structure, redundant signed digit (RSD) arithmetic, and fast radix-4 signed power-of-twos (SPT) conversion, we propose a high-speed LMS adaptive filter architecture with low hardware cost. With this architecture, good performance of adaptive filtering is still maintained. |
Year | DOI | Venue |
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1999 | 10.1109/ISCAS.1999.778816 | ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING |
Keywords | Field | DocType |
digital filters,adaptive filters,arithmetic,data processing,hardware,finite impulse response filter,adaptive filter,filtering,least squares approximation,computer architecture | Architecture,Digital filter,Control theory,Computer science,Electronic engineering,Kernel adaptive filter,Adaptive filter,Recursive least squares filter | Conference |
Citations | PageRank | References |
1 | 0.45 | 0 |
Authors | ||
1 |
Name | Order | Citations | PageRank |
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Hsiang-Feng Chi | 1 | 22 | 4.14 |