Title
Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors
Abstract
The floating point portion of the SPEC CPU suite and the HPC Challenge suite are widely recognized and utilized as benchmarks that represent scientific application behavior. In this work we show that while these benchmark suites may be representative of the cache behavior of production scientific applications, they do not accurately represent the TLB behavior of these applications. Furthermore, we demonstrate that the difference can have a significant impact on performance. In the first part of the paper we present results from implementation-independent trace-based simulations which demonstrate that benchmarks exhibit significantly different TLB behavior for a range of page sizes than a representative set of production applications. In the second part we validate these results on the AMD Opteron implementation of the x86 architecture, showing that false conclusions about choice of page size, drawn from benchmark performance, can result in performance degradations of up to nearly 50% for the production applications we investigated..
Year
DOI
Venue
2008
10.1109/ISPASS.2008.4510742
Austin, TX
Keywords
Field
DocType
cache behavior,different tlb behavior,tlb behavior,commodity microprocessors,hpc challenge suite,performance degradation,scientific application behavior,high-end scientific applications,benchmark performance,production application,production scientific application,page size,computer aided manufacturing,computer science,instruction set,application software,floating point arithmetic,government,instruction sets,x86 architecture,floating point,production,computational modeling,degradation
x86,Suite,Floating point,Cache,Instruction set,Computer science,Parallel computing,Page,Spec#,Translation lookaside buffer
Conference
ISBN
Citations 
PageRank 
978-1-4244-2233-3
25
1.41
References 
Authors
9
3
Name
Order
Citations
PageRank
Collin McCurdy142727.04
Alan L. Coxa2251.41
Jeffrey Vetter348129.54