Name
Abstract | ||
|---|---|---|
This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling ... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.883319 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Flash memory,CMOS technology,Memory architecture,Random access memory,Space technology,CMOS process,Voltage,Digital signal processing,Costs,Read-write memory | Journal | 41 |
Issue | ISSN | Citations |
11 | 0018-9200 | 6 |
PageRank | References | Authors |
1.27 | 1 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Ogura | 1 | 17 | 4.58 |
| M. Hosoda | 2 | 6 | 1.27 |
| T. Ogawa | 3 | 6 | 1.27 |
| T. Kato | 4 | 18 | 4.56 |
| A. Kanda | 5 | 7 | 2.02 |
| Toshio Fujisawa | 6 | 92 | 15.13 |
| S. Shimizu | 7 | 75 | 8.32 |
| M. Katsumata | 8 | 6 | 1.61 |