Title
A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays
Abstract
Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.<>
Year
DOI
Venue
1990
10.1109/2.48799
IEEE Computer
Keywords
DocType
Volume
major classes-set switching,replacement unit,time redundancy-are,processor switching,typical technique,Fault-Tolerant Processor Arrays,proposed taxonomy,reconfiguration technique,Reconfiguration Techniques,reconfiguration scheme,local redundancy,future research
Journal
23
Issue
ISSN
Citations 
1
0018-9162
60
PageRank 
References 
Authors
6.03
12
2
Name
Order
Citations
PageRank
Mengly Chean1606.03
Jose A. B. Fortes244652.01