Name
Abstract | ||
|---|---|---|
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1007/3-540-45716-X_35 | PATMOS |
Keywords | Field | DocType |
significant overestimation,main cause,postlayout effect,overall switching activity,cmos digital circuits,digital circuit,gate level,conventional logic simulator,activity overestimation,delay model,switching activity,accurate estimation,parasitic effect,digital circuits | Glitch,Digital electronics,Spice,Computer science,CMOS,Electronic engineering,Logic simulation,Estimation theory,Verilog,Integrated circuit | Conference |
ISBN | Citations | PageRank |
3-540-44143-3 | 4 | 0.48 |
References | Authors | |
6 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Baena | 1 | 4 | 0.48 |
| Jorge Juan-chico | 2 | 31 | 6.52 |
| Manuel J. Bellido | 3 | 82 | 11.82 |
| P. Ruiz-de-Clavijo | 4 | 5 | 1.19 |
| C. J. Jiménez | 5 | 30 | 5.48 |
| Manuel Valencia | 6 | 28 | 6.24 |