Name
Abstract | ||
|---|---|---|
Superpage and page coloring are two important practical techniques to improve the performance of Translation Lookaside Buffers (TLBs) and shared Last Level Cache (LLC) respectively. However, there exists a gap between these two techniques in current hardware-architecture design, resulting in the contradiction in adopting these two optimizations simultaneously: a superpage requires hundreds of contiguous (e.g. a power of two) base pages in both virtual and physical memory, which would compulsorily occupy all available page colors (or cache sets), thus making page coloring failed to work. This is because most contemporary architecture adopts the design with cache set indexes placed in the least significant part of block address. In this paper, we propose a lightweight approach named Scattered Superpage to bridge this gap. Scattered Superpage decouples a superpage from the limitation of occupying multiple contiguous physical base pages. A superpage is still contiguous in virtual memory, but it is scattered mapping into multiple physical superpages, and it just occupies specified partial page colors in each physical superpage, thus it allows us to configure page color for each superpage. The huge TLB is slightly modified to store page color configuration for each superpage and to calculate target physical address based on this configuration when doing address translation. The experimental results show that the Scattered Superpage can improve system performance by 20.51% and reduce unfairness by 27.77% in our 4-core simulation system (with multi-program memory-intensive workloads). It achieves this by reducing last level cache miss by 17.05% and reducing TLB miss by 86.02% simultaneously. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCD.2013.6657040 | ICCD |
Keywords | Field | DocType |
llc,tlb,cache storage,4-core simulation system,translation lookaside buffer performance,last level cache,hardware-architecture design,storage allocation,physical memory,block address,scattered superpage,virtual memory,superpage decoupling,multiprocessing systems,multiple contiguous physical base pages,address translation,unfairness reduction,optimization,physical address,tlb performance,cache set index,multiprogram memory-intensive workload,page color configuration,page coloring | Physical address,Simulation system,Computer science,Cache,Virtual memory,Parallel computing,Bridging (networking),Real-time computing,Cache coloring,Translation lookaside buffer,Operating system,Power of two | Conference |
Volume | Issue | Citations |
null | null | 3 |
PageRank | References | Authors |
0.38 | 30 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Licheng Chen | 1 | 103 | 9.74 |
| Yanan Wang | 2 | 22 | 2.57 |
| Zehan Cui | 3 | 197 | 10.00 |
| Yongbing Huang | 4 | 76 | 6.24 |
| Yungang Bao | 5 | 361 | 31.11 |
| Ming-yu Chen | 6 | 902 | 79.29 |