Name
Abstract | ||
|---|---|---|
The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the power of B method that guarantees the correct design (w.r.t. a formal specification). This allows avoiding the design test since it is "correct by proven construction". Furthermore, this project provides a tool, called BHDL, with a graphical interface for creating, editing, viewing and proving modular hardware architectures. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/CSD.2003.1207723 | ACSD |
Keywords | Field | DocType |
main goal,proven construction,digital circuit,b method,digital circuit design,design test,hardware architectures,hardware description languages,digital circuits,bhdl tool,vhdl,graphical user interfaces,hardware-software codesign,correct design,graphical interface,modular hardware architecture,formal specification,circuit design,design methodology,hardware architecture,formal specifications,computer languages,hardware | Formal equivalence checking,Computer architecture,Programming language,Computer science,Circuit design,Modular design,Formal methods,Register-transfer level,Physical design,BHDL,Hardware description language | Conference |
ISBN | Citations | PageRank |
0-7695-1887-7 | 6 | 0.66 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ammar Aljer | 1 | 10 | 1.16 |
| Philippe Devienne | 2 | 131 | 19.93 |
| Sophie Tison | 3 | 625 | 53.49 |
| Jean-louis Boulanger | 4 | 22 | 4.16 |
| Georges Mariano | 5 | 15 | 2.89 |