Name
Title | ||
|---|---|---|
Heuristic for two-level cache hierarchy exploration considering energy consumption and performance |
Abstract | ||
|---|---|---|
In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (Two-level Cache Exploration Heuristicconsidering CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/11847083_8 | PATMOS |
Keywords | Field | DocType |
two-level cache hierarchy,two-level cache hierarchy exploration,mibench suite,energy consumption,energy improvement,automated method,proposed heuristic,existing heuristic,embedded application,two-level cache memory hierarchy,two-level cache,cache memory | Cache-oblivious algorithm,Heuristic,Memory hierarchy,Cache pollution,CPU cache,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Energy consumption | Conference |
Volume | ISSN | ISBN |
4148 | 0302-9743 | 3-540-39094-4 |
Citations | PageRank | References |
13 | 0.84 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. G. Silva-Filho | 1 | 21 | 3.38 |
| F. R. Cordeiro | 2 | 46 | 7.14 |
| R. E. Sant'Anna | 3 | 13 | 0.84 |
| M. E. Lima | 4 | 14 | 1.55 |