Name
Title | ||
|---|---|---|
The Design and Implementation of a High Performance and High Flexibility Memory Interface Architecture for Embedded Application |
Abstract | ||
|---|---|---|
Two of the most significant factors in the success of todaypsilas system-on-chip (SoC) designs are the ability to deliver efficient access to off-chip high speed memory and the ability to be compatible with several different interface-timings of several different sorts of memories. This paper introduces a novel general external memory interface (GEMI) architecture for the high performance and high flexibility memory interface. Several techniques and methods, i.e. data and command buffers based on asynchronous FIFO, optimized bank management, multiple bus width adaptation, improved WISHBONE bus interface, optimized array-structure data accessing, are proposed in this paper for fulfilling the requirements mentioned above. And the performance improvement by using of our architecture and techniques is analyzed. At the end of the paper, the simulation and tape-out results are provided. The whole implementation of architecture is proven to be not only functional and efficient, but also flexible, programmable and reusable by simulation and silicon verification. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICYCS.2008.354 | ICYCS |
Keywords | Field | DocType |
efficient access,high performance,novel general external memory,optimized bank management,wishbone bus interface,array-structure data accessing,gemi,high flexibility memory interface,memory interface,high flexibility memory,embedded application,different interface-timings,improved wishbone bus interface,buffer storage,asynchronous fifo,different sort,system-on-chip,multiple bus width adaptation,general external memory interface architecture design,command buffer,high speed memory,logic design,interface architecture,optimized array-structure data accessing,bank management,memory architecture,peripheral interfaces,optimized array-structure data,wishbone,soc design,computer architecture,system on chip,chip,memory management,external memory,structured data,system on a chip | Logic synthesis,Wishbone,Computer architecture,Architecture,System on a chip,Computer science,Memory management,External memory interface,Memory architecture,Performance improvement,Embedded system | Conference |
ISBN | Citations | PageRank |
978-0-7695-3398-8 | 0 | 0.34 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hualong Zhao | 1 | 0 | 1.35 |
| Hongshi Sang | 2 | 0 | 1.01 |
| Tianxu Zhang | 3 | 206 | 23.18 |