Name
Abstract | ||
|---|---|---|
This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-mu n CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.1189 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
phase locked loops, divider, phase noise, fractional-N frequency synthesizer, dual modulus prescaler | Phase-locked loop,Frequency divider,Dual-modulus prescaler,Phase noise,Electronic engineering,Engineering | Journal |
Volume | Issue | ISSN |
E95C | 7 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hideyuki Nakamizo | 1 | 0 | 1.01 |
| Kenichi Tajima | 2 | 0 | 1.01 |
| Ryoji Hayashi | 3 | 3 | 2.54 |
| Kenji Kawakami | 4 | 0 | 0.68 |
| Toshiya Uozumi | 5 | 0 | 0.34 |