Name
Abstract | ||
|---|---|---|
This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transele.E94.C1061 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
SAR ADC, testing, DC linearity, design for testability, built-in self-test | Design for testing,Flight dynamics (spacecraft),Linearity testing,Linearity,Electronic engineering,Integrated circuit design,Engineering,Successive approximation ADC,Built-in self-test | Journal |
Volume | Issue | ISSN |
E94C | 6 | 1745-1353 |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomohiko Ogawa | 1 | 19 | 2.76 |
| Haruo Kobayashi | 2 | 1 | 0.37 |
| Satoshi Uemori | 3 | 10 | 3.24 |
| Yohei Tan | 4 | 9 | 2.86 |
| Satoshi Ito | 5 | 25 | 5.59 |
| Nobukazu Takai | 6 | 30 | 11.68 |
| Takahiro J. Yamaguchi | 7 | 176 | 35.24 |
| Kiichi Niitsu | 8 | 126 | 38.14 |