Name
Abstract | ||
|---|---|---|
This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm2 including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz ·2 ENOB /W . |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/JSSC.2010.2056830 | J. Solid-State Circuits |
Keywords | Field | DocType |
spurious free dynamic range,pipelined accumulator,voltage 1.2 v,dac-based ddfs,hybrid direct digital frequency synthesizer,nonlinear digital-to-analog converter,linear dac,digital-to-analog converter (dac),uhf integrated circuits,sfdr,cmos direct digital frequency synthesizer (ddfs),segmented nonlinear dac,size 90 nm,power 350 mw,direct digital synthesis,cmos digital integrated circuits,low-power ddfs,voltage 2.5 v,nyquist frequency,frequency 1.3 ghz,cmos chip,digital-analogue conversion,accuracy,decoding,chip,hardware,read only memory | Nyquist frequency,Computer science,CMOS,Effective number of bits,Frequency synthesizer,Spurious-free dynamic range,Chip,Electronic engineering,Direct digital synthesizer,Electrical engineering,Sine wave | Journal |
Volume | Issue | ISSN |
45 | 9 | 0018-9200 |
Citations | PageRank | References |
12 | 0.96 | 15 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hong Chang Yeoh | 1 | 22 | 2.49 |
| Jae-Hun Jung | 2 | 53 | 9.00 |
| Yun-Hwan Jung | 3 | 21 | 2.77 |
| Kwang-hyun Baek | 4 | 129 | 26.82 |