Title
An Emulator for Exploring RaPiD Configurable Computing Architectures
Abstract
The RaPiD project at the University of Washington has been studying configurable computing architectures optimized for coarse-grained data and computation units and deep computation pipelines. This research targets applications in the signal and image-processing domain since they make the greatest demand for computation and power in embedded and mobile computing applications, and these demands are increasing faster than Moore's law. This paper describes the RaPiD Emulator, a system that will allow the exploration of alternative configurable architectures in the context of benchmark applications running in real-time. The RaPiD emulator provides enough FPGA gates to implement large RaPiD arrays, along with a high-performance streaming memory architecture and high-bandwidth data interfaces to a host processor and external devices. Running at 50 MHz, the emulator is able to achieve over 1 GMACs/second.
Year
DOI
Venue
2001
10.1007/3-540-44687-7_3
FPL
Keywords
Field
DocType
exploring rapid configurable computing,high-bandwidth data interface,deep computation pipeline,large rapid array,alternative configurable architecture,rapid emulator,rapid project,computation unit,mobile computing application,configurable computing,coarse-grained data,mobile computer,real time,signal and image processing
Mobile computing,Signal processing,Data transmission,Computer science,Data stream,Parallel computing,Field-programmable gate array,Real-time computing,Control reconfiguration,Memory architecture,Embedded system,Memory module
Conference
ISBN
Citations 
PageRank 
3-540-42499-7
10
1.30
References 
Authors
5
10
Name
Order
Citations
PageRank
Chris Fisher1101.30
Kevin Rennie2101.30
Guanbin Xing31319.07
Stefan G. Berg4101.64
Kevin Bolding59734.93
John H. Naegle6101.64
Daniel Parshall7101.64
Dmitriy Portnov8212.62
Adnan Sulejmanpasic9101.30
Carl Ebeling101405185.32