Name
Abstract | ||
|---|---|---|
This paper presents an efficient layout-level synthesis approach for RF planar on-chip spiral inductors. A spiral inductor is modeled using artificial neural networks in which the layout design parameters, namely, spiral outer diameter, number of turns, width of metal traces, and metal spacing, are taken as input. Inductance, quality factor (Q), and self-resonance frequency (SRF) form the output of the neural model. Particle-swarm optimization is used to explore the layout space to achieve a given target inductance meeting the SRF and other constraints. Our synthesis approach provides multiple sets of layout parameters that help a designer in the tradeoff analysis between conflicting objectives, such as area, Q, and SRF for a target-inductance value. We present several synthesis results which show good accuracy with respect to full-wave electromagnetic (EM) simulations. Since the proposed procedure does not require an EM simulation in the synthesis loop, it substantially reduces the cycle time in RF-circuit design optimization. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCAD.2007.907284 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
spiral inductor,layout parameter,RF ICs,efficient layout-level synthesis approach,layout space,On-Chip Spiral Inductors,layout design parameter,RF planar on-chip spiral,PSO-Based Synthesis,synthesis loop,synthesis result,synthesis approach,spiral outer diameter | Journal | 27 |
Issue | ISSN | Citations |
1 | 0278-0070 | 20 |
PageRank | References | Authors |
1.47 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. K. Mandal | 1 | 20 | 1.47 |
| Shamik Sural | 2 | 1008 | 96.36 |
| A. Patra | 3 | 57 | 6.14 |