Name
Title | ||
|---|---|---|
Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment) |
Abstract | ||
|---|---|---|
Two designs have been presented for high throughput pipelined implementation using field-programmable gate arrays (FPGAs) of the advanced encryption standard (AES). Both are believed to be faster than the existing FPGA designs and achieve throughputs of 30 and 28 Gbps. The fastest design achieves a throughput, for either encipher or decipher, in excess of 30 Gbps using a Xilinx Spartan-III part an... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1049/iet-ifs:20060059 | IET Information Security |
Keywords | Field | DocType |
cryptography,field programmable gate arrays,logic design | Logic synthesis,Computer science,Advanced Encryption Standard,Block cipher mode of operation,Cryptography,Field-programmable gate array,Composite field,Throughput,Cycles per instruction,Embedded system | Journal |
Volume | Issue | ISSN |
1 | 1 | 1751-8709 |
Citations | PageRank | References |
18 | 0.89 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tim Good | 1 | 112 | 8.79 |
| M. Benaissa | 2 | 27 | 2.62 |