Paper Info
Title
Two-Stage Digital I/Q Demodulator Employing A Reconfigurable 16-Phase Down-Mixing Technique
Abstract
This letter presents a new two-stage digital I/Q demodulator employing a reconfigurable 16-phase quadrature intermediate frequency ( IF) sampling technique for multistandard wireless systems such as mobile TV applications. The proposed two-stage digital I/Q demodulator provides the flexibility for the multiphase scheme such as a quadrature phase shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at the level of down-mixing, which introduces an efficient architecture for the following decimation filter. In this letter, the prototype chip has been implemented in a 0.18 mu m standard CMOS technology and occupied with the active chip area of 0.02 mm(2). The power consumption of the fabricated chip is 0.42 mW with a 1.8V supply voltage at the sampling frequency of 26 MHz. The experimental results show that the proposed two-stage digital I/Q demodulator is suitable for multistandard wireless systems which require small silicon area and low power dissipation.
Year
DOI
Venue
2010
10.1587/elex.7.177
IEICE ELECTRONICS EXPRESS
Keywords
Field
DocType
demodulation, down-mixing, quadrature, sigma-delta
Demodulation,Decimation,Quadrature amplitude modulation,Computer science,QAM,Electronic engineering,Chip,Delta-sigma modulation,Amplitude modulation,Electrical engineering,Phase-shift keying
Journal
Volume
Issue
ISSN
7
3
1349-2543
Citations 
PageRank 
References 
0
0.34
2
Authors
3
Name
Order
Citations
PageRank
Chanyong Jeong120.85
Young-Jae Min2436.11
Soo-Won Kim311629.86