Title | ||
---|---|---|
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration |
Abstract | ||
---|---|---|
Increasing the number of cores in a multi-core processor can only be achieved by reducing the resources available in each
core, and hence sacrificing the per-core performance. Furthermore, having a large number of homogeneous cores may not be effective
for all the applications. For instance, threads with high instruction level parallelism will under-perform considerably in
the resource-constrained cores. In this paper, we propose a core architecture that can be adapted to improve a single thread’s
performance or to execute multiple threads. In particular, we integrate Reconfigurable Hardware Unit (RHU) in the resource-constrained
cores of a many-core processor. The RHU can be reconfigured to execute the frequently encountered instructions from a thread
in order to increase the core’s overall execution bandwidth, thus improving its performance. On the other hand, if the core’s
resources are sufficient for a thread, then the RHU can be configured to executed instructions from a different thread to
increase the thread level parallelism. The RHU has low area overhead, and hence has minimal impact on scalability of the number
of cores. To further limit the area overhead of this mechanism, generation of the reconfiguration bits for the RHUs of multiple
cores is delegated to a single core. In this paper, we present the results for using the RHU to improve a single thread’s
performance. Our experiments show that the proposed architecture improves the per-core performance by an average of about
23% across a wide range of applications. |
Year | DOI | Venue |
---|---|---|
2010 | 10.1007/s10766-010-0128-3 | International Journal of Parallel Programming |
Keywords | Field | DocType |
reconfigurable hardware,multi core processor,thread level parallelism | Instruction-level parallelism,Single-core,Computer science,Task parallelism,Parallel computing,Thread (computing),Bandwidth (signal processing),Control reconfiguration,Reconfigurable computing,Scalability | Journal |
Volume | Issue | ISSN |
38 | 3-4 | 1573-7640 |
Citations | PageRank | References |
0 | 0.34 | 33 |
Authors | ||
2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Tameesh Suri | 1 | 49 | 5.44 |
Aneesh Aggarwal | 2 | 202 | 16.91 |